Super computer on a ... chip

Scientists at the University of Texas, Austin, are inventing a completely new processor architecture, to solve one of the problems that chip designers are facing. If successful, their efforts, funded by the US Department of Defense, will bring microprocessors with unprecedented productivity and flexibility.

For decades, transistors' density on chips has doubled every two years; Thus the microprocessor is getting smaller and stronger. Advanced technologies such as guessing demand and predicting an upcoming executable command help chip designers increase chip processing speed, or force it to execute multiple lines at once. However, chips are increasingly complex, the heat it produces during operation signaling chip designers have reached the final threshold of this approach. They are switching to multi-core design on the same chip.

However, according to Professor Doug Burger of the University of Texas, the problem is that, in order for the software to take advantage of that multi-core structure, the programmer must write code so that the program can divide the processing task into multiple parts. and assigned to the staff to manipulate. For many applications, this is impossible or very difficult to write. " The computer industry is hitting the programming wall, throwing balls to the software side, hoping the programmer will write applications for the new system " - he said.

Professor Burger and colleagues hope to solve these problems with a new type of chip and command processing architecture called Tera-op Reliable Intelligently adaptive Processing System. "Our goal is to take advantage of concurrency performance, whether or not developers put it into application, " he said.

Trips uses some techniques to do that. First, Trips' compiler will send executable code lines into blocks containing up to 128 commands. The processor will receive and execute the whole block at the same time, as if it were a single command, thus reducing the processing burden or prioritizing processing.

Second, the command in a block executes in the " data flow " way, ie each command on arrival is processed immediately, not in the order specified by the programmer.

Another technique: In the same block, the Trips compiler can merge two commands on two different lines into one command if they have the same goal and the same way.

Finally, the implementation of the data flow is due to the " direct target execution " technique, in which the results of this command will be passed directly to the command that needs the result immediately and no longer be stored. temporary in the registry file as it is today. This will reduce the work pressure on the chip and significantly increase processing speed.

Compared to previous improvements to increase processing speed, the above techniques do not make the chip produce as much heat as before and consume less power.

Engineer Mark McDermott, who previously worked for Intel, is now Vice President of Coherent Logix in Austin, commented: " Just by looking at a chip like Pentium, you will see a lot of control transistors have no task at all - they just there and power consumption. The Trips generation chip is trying to put those complex structures into the compiler . " However, McDermott added, it is not known what the future of the Trips chip will be because scientists need to study more parameters.

According to developing scientists Trips, data flow techniques work well with three types of concurrent commands in the software and it can work well for many types of applications: Science, commerce and embedded software . This is why the US Department of Defense poured in this $ 15.4 million project because it hopes to have chips that process 1,000 billion orders per second.

The University of Texas is about to design Trips chips to IBM and it will produce prototype chips for delivery in February to next year. The chip will have two cores, running at 500MHz, which will execute 16 billion instructions per second. The university aims to commercialize this technology and achieve a chip speed of 10 GHz, processing 1,000 billion orders in 2012.

One of the major challenges for this project is compatibility with available software. One solution is to use Trips as chips parallel to older chips.