Will HP 'break' Moore's Law?

Researchers from the HP Labs lab expected this month to publish a specialized report on how to increase the performance of some processors, and reduce energy consumption by replacing sugar. communicate within the chip with micro nano networks .

As described in Moore's Law, chip makers can simultaneously increase processing efficiency and reduce processor cost by reducing the size of transistors and links (equal to the metal to connect the transistors).

However, reducing the size of these components has become increasingly complex and expensive. To do that, designers are forced to trade off between performance, energy efficiency and product cost.

Meanwhile, according to HP Labs senior director of quantum science research, Stan Williams, the replacement of traditional interconnection by architecture will dramatically change the formula set by Moore. .

According to him, when removing traditional connections, the size of the chips will be significantly reduced. Performance will increase, but maybe the chip will still have to rely on traditional transistors. Prices will certainly fall because new technology does not require people to invest millions of dollars in new microchip production equipment. In addition, it is certain that the energy consumption of the chip will decrease accordingly.

Interconnected

This method is one of the ideas that has appeared and been studied in HP Labs for many years. The company has also demonstrated how to use this structure to upgrade memory chips, reduce fabrication errors, and make circuits faster to calculate.

Although HP has long been not paying much attention to the chip business, it has focused a lot of resources on business from technology licensing. If the concept of knitting connections becomes a reality, HP can make hundreds of millions of dollars from royalty.

Currently, HP Labs only simulates a very small "programmable antenna network" (FPGA) with interconnected networks, and hopes that the standard device model will be completed later this year. Stan Williams predicted, by 2010, manufacturers could integrate interwoven communication systems for commercial chips.

Williams said HP Labs is researching a new concept with FPGA, whereby a chip can be programmed to perform many functions. In an FPGA device, different function blocks are directly connected to each other through links. Therefore, increasing the function blocks in the FPGA will increase the number of data lines passing.

Size problems

According to the assessment, the benefits from the new structure will be huge. For a dynamic communication network, certain function blocks or transistors can enter a state of "hibernation" when not being used, and thus reduce energy use.

HP estimates that an FPGA made of 45nm transistors (1nm = 1 / billion m) and 45nm nanowire network will be only 4% smaller than a standard FPGA manufactured on 45nm process.

The structure itself can be made of aluminum or copper circuits, which are smaller than today's connected ones. The issue of size reduction will also be solved by applying a new process called lithography.